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etd AT Indian Institute of Science >
Browsing by Advisor Govindarajan, R
Showing results 1 to 12 of 12
| Submitted Date | Title | Author(s) | Thesis Guide(s) | | 2004-06 | Compiler Techniques For Code Size And Power Reduction For Embedded Processors | Sarvani, V V N S | Govindarajan, R |
| 2011-11 | Compiler Transformations For Improving The Performance Of Software Transactional Memory | Mannarswamy, Sandya S | Govindarajan, R |
| 2008-07 | Comprehensive Path-sensitive Data-flow Analysis | Thakur, Aditya | Govindarajan, R |
| 2008-05 | Efficient Cache Organization For Application Specific And General Purpose Processors | Rajan, Kaushik | Govindarajan, R |
| 2009-07 | Efficient Compilation Of Stream Programs Onto Multi-cores With Accelerators | Udupa, Abhishek | Govindarajan, R |
| 1999-04 | Efficient Resource Usage Modelling | Ramanan, V Janaki | Govindarajan, R |
| 1999-01 | Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors | Valluri, Madhavi Gopal | Govindarajan, R |
| 2008-09 | On-Chip Memory Architecture Exploration Of Embedded System On Chip | Kumar, T S Rajesh | Govindarajan, R; Ravikumar, C P |
| 2006-12 | Performance Modeling And Evaluation Of Network Processors | Govind, S | Govindarajan, R |
| 2006-07 | Power-Aware Compilation Techniques For Embedded Systems | Shyam, K | Govindarajan, R |
| 2007-08 | Spill Code Minimization And Buffer And Code Size Aware Instruction Scheduling Techniques | Nagarakatte, Santosh G | Govindarajan, R |
| 2006-11 | A Systematic Approach To Synthesis Of Verification Test-Suites For Modular SoC Designs | Surendran, Sudhakar | Govindarajan, R |
Showing results 1 to 12 of 12
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