etd@IISc Collection:http://etd.iisc.ernet.in/2005/172018-06-27T04:21:12Z2018-06-27T04:21:12ZContent Dissemination in Mobile Ad Hoc NetworksPatra, Tapas Kumarhttp://etd.iisc.ernet.in/2005/37612018-06-26T11:21:12Z2018-06-25T18:30:00ZTitle: Content Dissemination in Mobile Ad Hoc Networks
Authors: Patra, Tapas Kumar
Abstract: In this thesis, we are concerned with content dissemination in mobile ad hoc networks. The scope of content dissemination is limited by network capacity, and sometimes the price to be paid for securing faster delivery. In the first part of the thesis, we address the issue of finding the maximum throughput that a mobile ad-hoc network can support. We have assumed that there is no price involved, and all nodes work as a team. The problem of determining the capacity region has long been known to be NP-hard even for stationary nodes. Mobility introduces an additional dimension of complexity because nodes now also have to decide when they should initiate route discovery. Since route discovery involves communication and computation overhead, it should not be invoked
very often. On the other hand, mobility implies that routes are bound to become stale, resulting in sub-optimal performance if routes are not updated. We attempt to gain some understanding of these effects by considering a simple one-dimensional network model. The simplicity of our model allows us to use stochastic dynamic programming (SDP) to find the maximum possible network throughput with ideal routing and medium access control (MAC) scheduling. Using the optimal value as a benchmark, we also propose and evaluate the performance of a simple threshold-based heuristic. Unlike the optimal policy which requires considerable state information, the proposed heuristic is simple to implement and is not overly sensitive to the threshold value. We find empirical conditions for our heuristic to be near-optimal. Also, network scenarios when our heuristic does not
perform very well are analyzed. We provide extensive numerical analysis and simulation results for different parameter settings of our model. Interestingly, we observe that in low density network the average throughput can first decrease with mobility, and then increase. This motivates us to study a mobile ad-hoc network when it is sparse and in a generalized environment, such as when movement of nodes is in a two-dimension plane. Due to sparseness, there are frequent disruptions in the connections and there may not be any end-to-end connection for delivery. The mobility of nodes may be used for carrying the forwarded message to the destination. This network is also known as a delay tolerant network. In the rest part of the thesis, we consider the relay nodes to be members of a group that charges a price for assisting in message transportation. First, we solve the problem of how to select first relay node when only one relay node can be chosen from a given number of groups. Next, we solve two problems, namely price-constrained delay minimization, and delay-constrained price optimization.2018-06-25T18:30:00ZSwitched Capacitive Filtering Scheme for Harmonic Suppression in Variable Speed AC DrivesPramanick, Sumit Kumarhttp://etd.iisc.ernet.in/2005/37352018-06-21T15:33:20Z2018-06-20T18:30:00ZTitle: Switched Capacitive Filtering Scheme for Harmonic Suppression in Variable Speed AC Drives
Authors: Pramanick, Sumit Kumar
Abstract: For low and medium power applications, conventional two-level inverters are widely used in industrial applications including electric vehicle drives, traction drives, distributed generation, power management and grid connected renewable energy systems. To filter out the harmonic currents from the load, passive line filters are used. These filters are designed to pass the fundamental phase current and suppress higher harmonic currents, making the filters bulky. To get a nearly sinusoidal current waveform, these two level inverters are switched at high frequency to shift the harmonic components in the phase current to high frequencies to reduce size and cost of the filter. But higher switching frequencies have some drawbacks like large dV /dt stresses on the motor terminals and switching devices, leading to electro-magnetic interference (EMI) problems and higher switching losses.
For full DC bus utilization to enhance the power output from the two level inverter, the inverter has to operate in overmodulation region up to the six-step operation. Considerable fifth and seventh order (6n ± 1, n = odd) harmonics are produced when the inverter operates in overmodulation region. These include some low order harmonics like fifth and seventh, which are currently suppressed by using bulky passive line filters. Different high frequency modulation schemes are uniquely used in overmodulation region to suppress these harmonics.
Another well accepted method of harmonic suppression is the selective harmonic elimination (SHE) techniques. SHE introduces notches at specific angles in a fundamental period of the inverter pole voltage to eliminate a particular harmonic component from the pole voltage. But, SHE involves extensive offline computation and requirement for higher memory for implementation of huge lookup tables. dodecagonal voltage space vectors have been reported in literature. Dodecagonal voltage space vector structures inherently eliminate fifth and seventh order (6n ± 1, n = odd) harmonics from the phase voltage. However, these require multiple isolated and unequal DC supplies (like VDC and 0.366VDC ). Generating DC voltage supplies at particular ratio to the main DC supply, requires additional circuitry. This increases the size of the converter and four quadrant back to back operation is not possible for the converter.
To overcome the problems mentioned above, a novel switched capacitive filtering technique is proposed in this work for low and medium power drives applications. The filtering is done by an inverter fed by capacitor. A novel method to ensure zero power contribution by an inverter is shown, enabling the inverter to be fed by a capacitor. Thus, the capacitor fed inverter is shown to operate as a switched capacitive filter, which generates harmonic voltages that gets eliminated from the phase voltage of conventional two level inverters. With the proposed switched capacitive filtering technique, the following benefits are achieved.
• Fifth and seventh order (6n ± 1, n = odd) harmonics are eliminated from the phase voltage, for the full modulation range of the two level inverters even while operating in overmodulation region and six-step mode. Thus, bulky passive line filters are avoided.
• Since, the capacitive filter does not contribute any active power to the load, single DC supply operation is possible. Hence, four quadrant back to back operations is possible with the proposed filtering technique.
• Dodecagonal voltage space vector structures are realized using single DC supply for the first time.
• Modulation techniques for different power circuit topologies have been proposed which inherently controls the capacitor voltage at specific voltage levels for the full modulation range of the inverter including six-step operation. Hence, no additional pre-charging circuitry is required.
• High frequency switching is shifted to the capacitive filter which is at a low voltage compared to the DC supply fed power contributing inverter. Thus, the main inverter need not be switched at high switching frequency for harmonic suppression. This reduces the switching loss as compared to conventional inverters, to achieve harmonic suppression of comparable order.
• Reduced voltage stress on the switches of the switched capacitive filter. Hence, low voltage devices can be used to implement the switched capacitive filter, reducing the cost and size drastically as compared to conventional passive line filters.
The proposed switched capacitive filtering scheme has been realized for open-end winding induction motor drive and three phase star connected three terminal induction motor drive where conventional two level inverter is used as the power contributing inverter. Additionally, extension of the capacitive filtering scheme to multilevel inverter fed drives is also shown, where the main power contributing inverter is a three level flying capacitor (FC) inverter. The power circuit implementations are briefly described as following.
(i) In open-end winding three phase induction motors, the two terminals of each of the three phase windings are accessed. The main DC bus connected two level inverter feeds power from one end of the motor terminals. A capacitor fed two level inverter eliminates the fifth and seventh order harmonics from the other end for the full modulation range including overmodulation and six-step operation of DC bus fed inverter. The voltage space vectors from both the inverters connected at opposite ends of the motor forms dodecagonal voltage space vectors. An uniform pulse width modulation (PWM), for the full modulation range is proposed which switches from the dodecagonal voltage space vectors while inherently maintaining the capacitor voltage at 0.289VDC .
(ii) In conventional star connection of three phase induction motors, all three terminals of the three phase windings are shorted from one end, leaving access to just three terminals. Such three terminal induction motor fed to conventional two level inverter is commonly used in many drives applications. Capacitor fed H-bridges are cascaded to such two-level inverters, to eliminate the fifth and seventh order harmonics from the phase voltage for the full modulation range including overmodulation and six-step operation of DC fed inverter. The voltage space vectors from capacitor fed H-bridges get added to the voltage space vectors from the two level inverter to form dodecagonal voltage space vectors. A PWM technique for the full modulation range is proposed to switch from the dodecagonal
voltage space vector while inherently maintaining the three H-bridge connected capacitor voltages at 0.1445VDC .
(iii) Advantages of dodecagonal space vector switching and multilevel inverters are achieved with a single DC supply. A DC supply fed three level flying capacitor (FC) inverter feeds active power to one end of the induction motor winding terminals and H-bridge connected capacitors eliminate fifth and seventh order harmonics from the other end of the motor winding terminals. The voltage space vectors from the three level FC inverter and the H-bridge inverter forms a three level dodecagonal voltage space vectors with symmetric triangular sectors. A PWM technique is developed to switch the three level dodecagonal space vectors and simultaneously control the H-bridge connected capacitors at 0.1445VDC . The fifth and seventh order harmonics are eliminated for the full modulation range of the three level FC inverter, including the extreme six-step operation. Additionally, the proposed inverter has also been shown to operate for rotor field oriented vector control of the open-end winding induction motor drive.
For all the power circuit implementation of the switched capacitive filter, an increase of 7.8% in the linear modulation range (up to 48.8Hz) is achieved, implying better DC bus utilization as compared to conventional inverter topologies switching from hexagonal voltage space vectors.
With advantages like fifth and seventh order (6n ± 1, n = odd) harmonic elimination throughout the modulation range, reduced dv/dt stress, lower switching frequency in high voltage devices, single DC supply requirement, dodecagonal voltage space vector switching, PWM technique with inherent capacitor balancing, increased linear modulation range and reduced voltage stress on high frequency switches, the proposed switched capacitive filtering scheme is well suited for low and medium power drives application with requirements for high dynamic performance and precise speed control.2018-06-20T18:30:00ZMultilevel Dodecagonal and Octadecagonal Voltage Space Vector Structures with a Single DC Supply Using Basic Inverter CellsBoby, Mathewshttp://etd.iisc.ernet.in/2005/37122018-06-15T11:47:05Z2018-06-14T18:30:00ZTitle: Multilevel Dodecagonal and Octadecagonal Voltage Space Vector Structures with a Single DC Supply Using Basic Inverter Cells
Authors: Boby, Mathews
Abstract: Multilevel converters have become the direct accepted solution for high power converter applications. They are used in wide variety of power electronic applications like power transmission and distribution, electric motor drives, battery management and renewable energy management to name a few. For medium and high voltage motor drives, especially induction motor drives, the use of multilevel voltage source inverters have become indispensible. A high voltage multilevel inverter could be realized using low voltage switching devices which are easily available and are of low cost. A multilevel inverter generates voltage waveforms of very low harmonic distortion by switching between voltage levels of reasonably small amplitude differences. Thus the dv/dt of the output voltage waveform is small and hence the electromagnetic interference generated is less. Because of better quality output generation, the switching frequency of the multilevel inverters could be reduced to control the losses. Thus, a multilevel converter stands definitely a class apart in terms of performance from a conventional two-level inverter. Many multilevel inverter topologies for induction motor drives are available in the literature. The basic multilevel topologies are the neutral point clamped (NPC) inverter, flying capacitor (FC) inverter and the cascaded H-bridge (CHB) inverter. Various other hybrid multilevel topologies have been proposed by using the basic multilevel inverter topologies. It is also possible to obtain multilevel output by using conventional two-level inverters feeding an open-end winding induction motor from both sides.
All the conventional multilevel voltage source inverters generate hexagonal (6 sided polygons) voltage space vector structures. When an inverter with hexagonal space vector structure is operated in the over modulation range, significant low order harmonics are generated in the phase voltage output. Over modulation operation is required for the full utilization of the available DC-link voltage and hence maximum power generation. Among the harmonics generated, the fifth and seventh harmonics are of significant magnitudes. These harmonics generate torque ripple in the motor output and are undesirable in high performance motor drive applications. The presence of these harmonics further creates problems in the closed loop current control of a motor, affecting the dynamic performance. Again, the harmonic currents generate losses in the stator windings. Therefore, in short, the presence of harmonic voltages in the inverter output is undesirable.
Many methods have been proposed to eliminate or mitigate the effect of the harmonics. One solution is to operate the inverter at high switching frequency and thereby push the harmonics generated to high frequencies. The stator leakage inductance offers high impedance to the high frequency harmonics and thus the harmonic currents generated are negligible. But, high switching frequency brings switching losses and high electromagnetic interference generation in the drive system. And also, high switching frequency operation is effective only in the linear modulation range. Another solution is to use passive harmonic filters at the inverter output. For low order harmonics, the filter components would be bulky and costly. The loss created by the filters degrades the efficiency of the drive system as well. The presence of a filter also affects the dynamic performance of the drive system during closed loop operation. Special pulse width modulation (PWM) techniques like selective harmonic elimination (SHE) PWM can prevent the generation of a particular harmonic from the phase voltage output. The disadvantages of such schemes are limited modulation index, poor dynamic performance and extensive offline computations. An elegant harmonic elimination method is to generate a voltage space vector structure having more number of sides like a dodecagon (12 sided polygons) or an octadecagon (18 sided polygons) rather than a hexagon.
Inverter topologies generating dodecagonal voltage space vector structure eliminate fifth and seventh order harmonics, represented as 6n 1; n = odd harmonics, from the phase voltages and hence from the motor phase currents, throughout the entire modulation range. The first harmonics appearing the phase voltage are the 11th and 13th harmonics. Another advantage is the increased linear modulation range of operation for a given DC-link voltage, because geometrically dodecagon is closer to circle than a hexagon. An octadecagonal structure eliminates the 11th and 13th harmonics as well from the phase voltage output. The harmonics present in the phase voltage are of the order 18n 1; n = 1; 2; 3; :::. Thus the total harmonics distortion (THD) of the phase voltage is further improved. The linear modulation range also gets enhanced compared to hexagonal and dodecagonal structures. Multilevel dodecagonal and octadecagonal space vector structures combines the advantages of both multilevel structure and dodecagonal and octadecagonal structure and hence are very attractive solutions for high performance induction motor drive schemes. Chapter 1 of this thesis introduces the multilevel in-verter topologies generating hexagonal, dodecagonal and octadecagonal voltage space vector structures. Inverter topologies generating multilevel dodecagonal and octadecago-nal voltage space vector structures have been proposed before but using multiple DC sources delivering active power. The presence of more than one DC source in the inverter topology makes the back to back operation (four-quadrant operation) of the drive system diﬃcult. And also the drive system becomes more costly and bulky. This thesis proposes induction motor drive schemes generating multilevel dodecagonal and octadecagonal volt-age space vector structures using a single DC source.
In Chapter 2, an induction motor drive scheme generating a six-concentric multilevel dodecagonal voltage space vector structure using a single DC source is proposed for an open-end winding induction motor. In the topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a DC source (Vdc) which delivers the entire active power, whereas the secondary inverter DC-link is maintained by a capacitor at a voltage of 0:289Vdc, which is self-balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small DC-link voltage. Hence, switching losses are small for both primary and secondary inverters. An open-loop V/f scheme was used to test the topology and modulation scheme.
In the work proposed in Chapter 3, the topology and modulation scheme used in the first work is modified for a star connected induction motor. Again, the scheme uses only a single DC source and generates a six-concentric multilevel space vector struc-ture. The power circuit topology is realized using a three-level flying capacitor (FC) inverter cascaded with an H-bridge (CHB). The capacitors in the CHB inverter are maintained at a voltage level of 0:1445Vdc. The FC inverter switches between volt-age levels of [Vdc; 0:5Vdc; 0] and the CHB inverter switches between voltage levels of [+01445Vdc; 0; 0:1445Vdc]. The PWM scheme generates a quasi-square waveform output from the FC inverter. This results in very few switchings of the FC inverter in a funda-mental cycle and hence the switching losses are controlled. The CHB inverter switches Ch. 0: at high frequency compared to the FC inverter and cancels the low order harmonics (6n 1; n = odd) generated by the FC inverter. Even though the CHB operates at higher switching frequency, the switchings are at low voltage thereby controlling the losses. The linear modulation range of operation is extended to 48:8Hz for a base frequency of 50Hz. An open-loop V/f scheme was used to test the topology and modulation scheme.
In Chapter 4, a nine-concentric multilevel octadecagonal space vector structure is proposed for the first time, again using a single DC source. The circuit topology remains same as the work in Chapter 3, except that the CHB capacitor voltage is maintained at 0:1895Vdc. The 5th; 7th; 11th and 13th harmonics are eliminated from the phase voltage output. The linear modulation range is enhanced to 49:5Hz for a base speed of 50Hz. An open-loop V/f scheme and rotor field oriented control scheme were used to test the proposed drive system.
All the proposed drive schemes have been extensively simulated and tested in hard-ware. Simulation was performed in MATLAB-SIMULINK environment. For implement-ing the inverter topology, SKM75GB12T4 IGBT modules were used. The control al-gorithms were implemented using a DSP (TI’s TMS320F28334) and an FPGA (Xilinx Spartan XC3S200). A 1kW , 415V , 4-pole induction motor was used for the experiment purpose.
The above mentioned induction motor drive schemes generate phase voltage outputs in which the low order harmonics are absent. The linear modulation range is extended near to the base frequency of operation compared to hexagonal space vector structure. In the inverter topologies, the secondary inverters or the CHB inverters functions as harmonic filters and delivers zero active power. The primary inverter in the topologies switches at low frequency, reducing the power loss. Single DC source requirement brings down the cost of the system as well as permitting easy four-quadrant operation. This is also advantageous in battery operated systems like EV applications. With these features and advantages, the proposed drive schemes are suitable for high performance, medium voltage induction motor drive applications.2018-06-14T18:30:00ZAtomistic Study of Carrier Transmission in Hetero-phase MoS2 StructuresSaha, Dipankarhttp://etd.iisc.ernet.in/2005/36222018-05-25T14:43:13Z2018-05-24T18:30:00ZTitle: Atomistic Study of Carrier Transmission in Hetero-phase MoS2 Structures
Authors: Saha, Dipankar
Abstract: In recent years, the use of first-principles based atomistic modeling technique has become extremely popular to gain better insights on the various locally modulated electronic properties of nano materials and structures. Atomistic modeling offers the benefit of predicting crystal structures, visualizing orbital distribution and electron density, as well as understanding material properties which are hard to access experimentally.
The single layer MoS2 has emerged as a suitable choice for the next generation nano devices, owing to its distinctive electrical, optical and mechanical properties like, better electrostatics, increased photo luminescence, higher mechanical flexibility, etc. The realization of decananometer scale digital switches with the single layer MoS2 as the channel may provide many significant advantages such as, high On/Off current ratio, excellent electrostatic control of the gate, low leakage, etc.
However, there are quite a few critical issues such as, forming low resistance source/drain contacts, achieving higher effective mobility, ensuring large scale controlled growth, etc. which need to be addressed for successful implementation of the atomically thin transistors in integrated circuits. Recent experimental demonstration showing the coexistence of metallic and semiconducting phases in the same monolayer MoS2, has attracted much attention for its use in ultra-low contact resistance-MoS2 transistors. Howbeit, the electronic structures of the metallic-to-semiconducting phase boundaries, which appear to dictate the carrier injection in such transistors, are not yet well understood.
In this work, we first develop the geometrically optimized atomistic models of the 2H-1T′ hetero-phase structures with two distinct phase boundaries, β and γ. We then apply density functional theory to calculate the electronic structures for those optimized geometries. Furthermore, we employ non equilibrium Green’s function formalism to evaluate the transmission spectra and the local density of states in order to assess the Schottky barrier nature of the phase boundaries.
Nonetheless, the symmetry of the source-channel and drain-channel junction, is a unique property of a metal-oxide semiconductor field effect transistor (MOSFET), which needs to be preserved while realizing sub-10 nm channel length devices using advanced technology. Employing experimental-findings-driven atomistic modeling technique, we demonstrate that such symmetry might not be preserved in an atomically thin phase-engineered MoS2- based MOSFET. It originates from the two distinct atomic patterns at phase boundaries (β and β*) when the semiconducting phase (channel) is sandwiched between the two metallic phases (source and drain).
Next, using first principles based quantum transport calculations we demonstrate that due to the clusterization of “Mo” atoms in 1T′ MoS2, the transmission along the zigzag direction is significantly higher than that in the armchair direction. Moreover, to achieve excellent impedance matching with various metal contacts (such as, “Au”, “Pd”, etc.), we further develop the atomistic models of metal-1T′ MoS2 edge contact geometries and compute their resistance values.
Other than the charge carrier transport, analysing the heat transport across the channel is also crucial in designing the ultra-thin next generation transistors. Hence, in this thesis work, we have investigated the electro-thermal transport properties of single layer MoS2, in quasi ballistic regime. Besides the perfect monolayer in its pristine form, we have also considered various line defects which have been experimentally observed in mechanically exfoliated MoS2 samples. Furthermore, a comprehensive study on the phonon thermal conductivity of a suspended monolayer MoS2, has been incorporated in this thesis.
The studies presented in this thesis could be useful for understanding the carrier transport in atomically thin devices and designing the ultra-thin next generation transistors.2018-05-24T18:30:00Z