etd@IISc Collection:http://hdl.handle.net/2005/172015-11-28T15:21:20Z2015-11-28T15:21:20ZCompact Modeling Of Asymmetric/Independent Double Gate MOSFETSrivatsava, Jhttp://hdl.handle.net/2005/23462014-07-18T07:16:54Z2014-07-17T18:30:00ZTitle: Compact Modeling Of Asymmetric/Independent Double Gate MOSFET
Authors: Srivatsava, J
Abstract: For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs (MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk-MOSFET, an accurate and physical compact model is important for MuGFET based circuit design.
Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET(DGFET),as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thicknesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG(IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge.
We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two conﬁgurations1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG(IDG)MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate(DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device.
We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demonstrate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible.
An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design(TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.2014-07-17T18:30:00ZIntegrated Magnetics Based DC-DC Converter Topologies For A DC Micro-GridDeepak, Ghttp://hdl.handle.net/2005/23102014-05-09T07:15:04Z2014-05-08T18:30:00ZTitle: Integrated Magnetics Based DC-DC Converter Topologies For A DC Micro-Grid
Authors: Deepak, G
Abstract: In the present day, owing to the increasing number of electronic loads such as computer power supplies, Compact fluorescent lamps (CFL) and the increasing number of sources such as solar photovoltaics, fuel cells (DC sources), DC Micro-grids provide a more efficient solution compared to the AC counterpart in terms of the number of stages involved in conversion. Also, the ability to be readily buffered to storage elements is an advantage in a DC system. Apart from this, there are no issues of frequency stability, reactive power transfer and ac power losses.
A DC micro-grid is effectively a multi-port dc-dc converter. The ports refer to the various sources and loads that are part of the micro-grid. Sources could be unidirectional (as in the case of PV, load) or bidirectional (as in the case of batteries). Interfacing a variety of ports and controlling power flow between these ports presents an interesting challenge.
Commonly used topologies interface the various ports at the DC bus capacitor thereby making the DC bus capacitor bulky. Apart from this, the DC bus coupled topologies route power from one port to another via the central capacitor. This increases the number of stages in transferring power from one port to another. An alternative topology is to use the active bridge type converters where dynamic power flow equations are required to control inter-port power flow. But, as the number of stages increase, the computations get tedious.In this thesis, a novel topology is proposed that uses a UU type transformer core to interface all the power ports. This alleviates the problems faced in the DC bus coupled topologies. A PWM scheme to control simultaneous power flow from each of the ports is also proposed in this thesis. The PWM scheme enables the usage of simple constant frequency average current mode control to dynamically control power sharing ratio between the various ports delivering to loads. By means of the proposed PWM scheme and the control scheme, the drawbacks of the active bridge topologies are alleviated. Using the proposed topology and the PWM scheme, a prototype micro-grid system is developed for a system comprising of the utility grid, batteries, solar PVs and resistive loads. Yet another aspect of the thesis explores the concept of connecting multiple micro-grids in order to create a 'local power network'. A potential application for this could be in interconnecting residential buildings and routing power from one house to another in order to balance demand and supply among these houses. This is against the growing trend of using the utility grid to also sink power and subsequently route it to other houses connected to the grid. Unfortunately not all areas have access to the utility grid. Additionally, turning the grid bidirectional requires that a number of standards be met and policies be created. But, the standard for using a local network that only involves a unidirectional grid is fixed by the community that owns such a network. In a crude sense, this scenario can be compared to the existence of a local area network to transfer information among users of the network. In this thesis, a prototype local power network interconnecting two micro-grids has been implemented.2014-05-08T18:30:00ZPhysics Based Analytical Thermal Conductivity Model For Metallic Single Walled Carbon NanotubeRex, Ahttp://hdl.handle.net/2005/20962013-07-02T11:40:35Z2013-07-01T18:30:00ZTitle: Physics Based Analytical Thermal Conductivity Model For Metallic Single Walled Carbon Nanotube
Authors: Rex, A
Abstract: Single-Walled Carbon Nanotube (SWCNT) based Very Large Scale Integrated circuit (VLSI) interconnect is one of the emerging technologies, and has the potential to overcome the thermal issues persisting even with the advanced copper based interconnect. This is because of it’s promising electrical and thermal transport properties. It can be stated that thermal energy transport in SWCNTs is highly anisotropic due to the quasi one dimensionality, and like in other allotropes of carbon, phonons are the dominant energy carriers of heat conduction. In case of conventional interconnect materials, copper and aluminium, although their thermal conductivity varies over orders of magnitude at temperatures below100 K, near room temperature and above they have almost constant value. On the other hand, the reported experimental studies on suspended metallic SWCNTs illustrate a wide variation of the longitudinal lattice thermal conductivity (κl) with respect to the temperature(T)and the tube length(L)at low, room and high temperatures. Physics based analytical formulation of κl of metallic SWCNT as a function of L and T is essential to efficiently quantify this emerging technology’s impact on the rising thermal management issues of Integrated Circuits.
In this work, a physics based diameter independent analytical model for κl of metallic SWCNT is addressed as a function of Lover a wide range of T. Heat conduction in metallic SWCNTs is governed by three resistive phonon scattering processes; second order three phonon Umklapp scattering, mass difference scattering and boundary scattering. For this study, all the above processes are considered, and the effective mode dependent relaxation time is determined by the Matthiessen’s rule. Phonon Boltzmann transport equation under the single mode relaxation time approximation is employed to derive the non-equilibrium distribution function. The heat flux as a function of temperature gradient is obtained from this non-equilibrium distribution function. Based on the Fourier’s definition of thermal conductivity, κl of metallic SWCNT is formulated and the Debye approximations are used to arrive at analytical model.
The model developed is validated against both the low and high temperature experimental investigations. At low temperatures, thermal resistance of metallic SWCNT is due to phonon-boundary scattering process, while at high temperatures it is governed by three phonon Umklapp scattering process. It is understood that apart from form factor due to mass difference scattering, boundary scattering also plays the key role in determining the peak value. At room temperature, κl of metallic SWCNT is found to be an order of magnitude higher than that of most of metals. The reason can be attributed to the fact that both sound velocity and Debye temperature which have direct effect on the phonon transport in a solid, are reasonably higher in SWCNTs. Though Umk lapp processes reduce the κl steeper than 1/T beyond room-temperature, it’s magnitude is round1000 W/m/K upto 800 K for various tube lengths, which confirms that this novel material is indeed an efficient conductor of heat also, at room-temperature and above.2013-07-01T18:30:00ZA Polymorphic Finite Field MultiplierDas, Saptarsihttp://hdl.handle.net/2005/21002013-07-03T06:37:38Z2013-07-02T18:30:00ZTitle: A Polymorphic Finite Field Multiplier
Authors: Das, Saptarsi
Abstract: Cryptography algorithms like the Advanced Encryption Standard, Elliptic Curve Cryptography algorithms etc are designed using algebraic properties of finite fields. Thus performance of these algorithms depend on performance of the underneath field operations. Moreover, different algorithms use finite fields of widely varying order. In order to cater to these finite fields of different orders in an area efficient manner, it is necessary to design solutions in the form of hardware-consolidations, keeping the performance requirements in mind. Due to their small area occupancy and high utilization, such circuits are less likely to stay idle and therefore are less prone to loss of energy due to leakage power dissipation. There is another class of applications that rely on finite field algebra namely the various error detection and correction techniques. Most of the classical block codes used for detection of bit-error in communications over noisy communication channels apply the algebraic properties of finite fields. Cyclic redundancy check is one such algorithm used for detection of error in data in computer network. Reed-Solomon code is most notable among classical block codes because of its widespread use in storage devices like CD, DVD, HDD etc.
In this work we present the architecture of a polymorphic multiplier for operations over various extensions of GF(2). We evolved the architecture of a textbook shift-and-add multiplier to arrive at the architecture of the polymorphic multiplier through a generalized mathematical formulation. The polymorphic multiplier is capable of morphing itself in runtime to create data-paths for multiplications of various orders. In order to optimally exploit the resources, we also introduced the capability of sub-word parallel execution in the polymorphic multiplier. The synthesis results of an instance of such a polymorphic multipliershowsabout41% savings in area with 21% degradation in maximum operating frequency compared to a collection of dedicated multipliers with equivalent functionality. We introduced the multiplier as an accelerator unit for field operations in the coarse grained runtime reconfigurable platform called REDEFINE. We observed about 40-50% improvement in performance of the AES algorithm and about 52×improvement in performance of Karatsuba-Ofman multiplication algorithm.2013-07-02T18:30:00Z