etd@IISc Collection:http://hdl.handle.net/2005/172017-03-21T12:00:13Z2017-03-21T12:00:13ZSecuring Multiprocessor Systems-on-ChipBiswas, Arnab Kumarhttp://hdl.handle.net/2005/25542016-09-08T07:08:11Z2016-09-07T18:30:00ZTitle: Securing Multiprocessor Systems-on-Chip
Authors: Biswas, Arnab Kumar
Abstract: With Multiprocessor Systems-on-Chips (MPSoCs) pervading our lives, security issues are emerging as a serious problem and attacks against these systems are becoming more critical and sophisticated. We have designed and implemented different hardware based solutions to ensure security of an MPSoC. Security assisting modules can be implemented at different abstraction
levels of an MPSoC design. We propose solutions both at circuit level and system level of abstractions. At the VLSI circuit level abstraction, we consider the problem of presence of noise voltage in input signal coming from outside world. This noise voltage disturbs the normal circuit operation inside a chip causing false logic reception. If the disturbance is caused
intentionally the security of a chip may be compromised causing glitch/transient attack. We propose an input receiver with hysteresis characteristic that can work at voltage levels between 0.9V and 5V. The circuit can protect the MPSoC from glitch/transient attack. At the system level, we propose solutions targeting Network-on-Chip (NoC) as the on-chip communication medium. We survey the possible attack scenarios on present-day MPSoCs and investigate a new attack scenario, i.e., router attack targeted toward NoC enabled MPSoC. We propose different monitoring-based countermeasures against routing table-based router attack in an MPSoC having multiple Trusted Execution Environments (TEEs). Software attacks, the most common type of attacks, mainly exploit vulnerabilities like buffer overflow. This is possible if proper access control to memory is absent in the system. We propose four hardware based mechanisms to implement Role Based Access Control (RBAC) model in NoC based MPSoC.2016-09-07T18:30:00ZInvestigation On Dodecagonal Multilevel Voltage Space Vector Structures By Cascading Flying Capacitor And Floating H-Bridge Cells For Medium Voltage IM DrivesMathew, Jaisonhttp://hdl.handle.net/2005/26002017-02-16T10:17:47Z2017-02-15T18:30:00ZTitle: Investigation On Dodecagonal Multilevel Voltage Space Vector Structures By Cascading Flying Capacitor And Floating H-Bridge Cells For Medium Voltage IM Drives
Authors: Mathew, Jaison
Abstract: In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of sub-harmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutral-point-clamped (NPC) inverters, cascaded H-bridge, and flying-capacitor multilevel inverters are some of the popular schemes used for high-power applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter-1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic two-level VSI topology.
The inverters used in motor drive applications have to be operated in over-modulation range in order to extract the maximum fundamental output voltage that is possible from the dc-link. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these low-order harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these low-order harmonics and non-linear PWM operation in over-modulation region, frequent over-current fault conditions occur and reliability of the drive is jeopardized. The twelve sided-polygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal space-vector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform.
Most of the previous works of dodecagonal space-vector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutral-point voltage fluctuation and the neutral-point voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal space-vector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point charge-balancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors.
For the speed control of induction motors, the space-vector PWM scheme is more advantageous than the sine-triangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional space-vector PWM is that the trigonometric operations demand formidable computational efforts and look-up tables. Carrier based, common-mode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. In-formation regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is pro-posed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large look-up tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrier-based methods).
The open-end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal space-vector structures relied on induction motors with open-end windings. The main disadvantage of open-end winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter-2 of this thesis uses open-end winding motor with flying-capacitor inverters for the generation of dodecagonal space-vectors, the topology presented in chapter-3 utilizes a cascade connection of flying-capacitors and floating H-bridge cells to generate the same set of voltage space-vectors, thus allowing any standard induction motor as the load.
Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage space-vector based multilevel inverter drives. In chapter-4 of the thesis, this aspect is taken into ac-count and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter-2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance.
The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a four-pole, 3.7kW, 50Hz, 415V three-phase induction motor was used as the load. Since the PWM ports are limited in a DSP, a ﬁeld-programmable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the dead-time signals for the power devices also.2017-02-15T18:30:00ZDevelopment Of Micromachined And Meso-Scale Multi-Axis Accelerometers With Displacement-Amplifying Compliant MechanismsKhan, Sambuddhahttp://hdl.handle.net/2005/26022017-02-22T09:44:39Z2017-02-21T18:30:00ZTitle: Development Of Micromachined And Meso-Scale Multi-Axis Accelerometers With Displacement-Amplifying Compliant Mechanisms
Authors: Khan, Sambuddha
Abstract: Simultaneously achieving high-sensitivity and a large resonance frequency of micromachined accelerometers is difficult because of the inherent trade-off between the two. In this thesis, we present a mechanical displacement-amplifying technique that is amenable to micromachining to enhance sensitivity without compromising on the resonance frequency and cross-axis sensitivity. Depending on the requirements of sensitivity alone or sensitivity and resonance frequency, Displacement-amplifying Compliant Mechanisms (DaCMs) are designed using the selection map-based technique, which indicates the limits of what is possible for given specifications on size and microfabrication.
In order to prove the benefits of a DaCM, we modified the designs of two very sensitive capacitive micromachined accelerometers from the literature by incorporating DaCMs and showed that, within the same footprint on the chip, the displacement sensitivity could be enhanced by more than 60% while the resonance frequency was also improved by more than 30%. As the focus of the thesis is to explore the integration of DaCMs into accelerometers, the analytical, computational, and practical aspects are discussed in detail. Both single and dual axis in-plane accelerometers are considered. The fabrication processes used are Silicon-on-Insulator Multi-user MEMS Processes (SOIMUMPs) and a customized Silicon-on-Insulator (SOI) based process. The fabricated accelerometers are packaged and brought to the product form. They were tested at the die level as well as in the packaged form.
Under dynamic conditions, the measured amplification factor of the fabricated single-axis in-plane accelerometer was observed to be 11. The overall dimension of the accelerometer was 4.25 mm × 1.25 mm. The first in-plane natural frequency of the fabricated accelerometer was found to be 6.25 kHz. The voltage sensitivity of the packaged accelerometer with the DaCM measured 26.7 mV/g at 40 Hz with differential capacitance sensitivity of 3926 ppm/g around the base capacitance of 0.75 pF.
The fabricated dual-axis accelerometer has a special configuration of twelve folded-beam suspension blocks that de-couple any displacements along the two in-plane orthogonal axes. The decoupling feature is retained even after adding the DaCMs along both the axes. The total device size was 8.6 mm × 8.6 mm. The device was also fabricated and packaged inside a ceramic flat-pin package using hybrid die-to-die wire-bonding. Die-level dynamic characterization showed that the average geometric advantage achieved using the DaCMs is 6.2 along both the in-plane axes. The measured axial voltage sensitivity of about 580 mV/g for both the axes was achieved with a cross-axial sensitivity of less than 2% and a natural frequency of 920 Hz. The static capacitance sensitivity was found to be 0.296 × 106 ppm/g with a base capacitance of 0.977 pF. Also presented in this work is a wide-band dual-axis accelerometer without an amplifying mechanism. Its first two in-plane modal frequencies measured 14.2 kHz. The measured sensitivity of the packaged accelerometer along both the axes of the device was found to be 62 mV/g at 200 Hz.
Aiming at towards cost-effective accelerometers for small-volume markets, we also developed a single-axis and two dual-axis meso-scale spring-steel in-plane accelerometers equipped with Allegro A1395 linear Hall-effect sensors for sensing the displacement of the proof-mass. The single-axis in-plane meso-scale accelerometer also contains a DaCM. It is observed through simulation that the single-axis design with a DaCM is 39% more sensitive and has 41% more bandwidth compared to a single-axis design without a DaCM. The measured sensitivity of the fabricated single-axis spring-steel accelerometer with a DaCM was found to be 71.4 mV/g with a minimum resolvable acceleration of 14 milli-g. The unique features of the first generation of dual-axis accelerometers are that a rechargeable Li-ion battery adds to the proof-mass. It also contains a de-coupling mechanism that can decompose any planar acceleration into its axial components. The second generation of dual-axis accelerometers is more compact in size. All the mechanical elements of the accelerometers are made of EN J42/AISI 1080 spring steel foil machined using Wire-cut Electro-Discharge- Machining. The measured sensitivity of the first generation of dual-axis meso-scale accelerometers is 78 and 108 mV/g along the X and Y axes whereas the second generation device exhibits a sensitivity of 40 mV/g for both the axes. The thesis concludes that the sensitivity of a displacement-based sensor can be improved using a suitably designed DaCM without compromising the resonance frequency and hence the bandwidth. Furthermore, the work describing the development of meso-scale accelerometers also establishes spring steel as a viable material for meso-scale applications.2017-02-21T18:30:00ZCompact Modeling Of Asymmetric/Independent Double Gate MOSFETSrivatsava, Jhttp://hdl.handle.net/2005/23462014-07-18T07:16:54Z2014-07-17T18:30:00ZTitle: Compact Modeling Of Asymmetric/Independent Double Gate MOSFET
Authors: Srivatsava, J
Abstract: For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs (MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk-MOSFET, an accurate and physical compact model is important for MuGFET based circuit design.
Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET(DGFET),as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thicknesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG(IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge.
We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two conﬁgurations1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG(IDG)MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate(DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device.
We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demonstrate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible.
An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design(TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.2014-07-17T18:30:00Z