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http://hdl.handle.net/2005/1
2018-02-23T00:03:28ZLow Power and Low Area Techniques for Neural Recording Application
http://hdl.handle.net/2005/3167
Title: Low Power and Low Area Techniques for Neural Recording Application
Authors: Chaturvedi, Vikram
Abstract: Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and to elucidate human neurophysiology. The advent of multi-channel micro-electrode arrays has driven the need for electronic store cord neural signals from many neurons. The continuous increase in demand of data from more number of neurons is challenging for the design of an efficient neural recording frontend(NRFE). Power consumption per channel and data rate minimization are two key problems which need to be addressed by next generation of neural recording systems. Area consumption per channel must be low for small implant size. Dynamic range in NRFE can vary with time due to change in electrode-neuron distance or background noise which demands adaptability. In this thesis, techniques to reduce power-per-channel and area-per-channel in a NRFE, via new circuits and architectures, are proposed.
An area efficient low power neural LNA is presented in UMC 0.13 μm 1P8M CMOS technology. The amplifier can be biased adaptively from 200 nA to 2 μA , modulating input referred noise from 9.92 μV to 3.9μV . We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier. It obviates the need of large input coupling capacitance in the amplifier which saves considerable amount of chip area. In vitro experiments were performed to validate the applicability of the neural LNA in neural recording systems.
ADC is another important block in a NRFE. An 8-bit SAR ADC along with the input and reference buffer is implemented in 0.13 μm CMOS technology. The use of ping-pong input sampling is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the output data rate, the A/D process is only enabled through a proposed activity dependent A/D scheme which ensures that the background noise is not processed. Based on the dynamic range requirement, the ADC resolution is adjusted from 8 to 1 bit at 1 bit step to reduce power consumption linearly. The ADC consumes 8.8 μW from1Vsupply at1MS/s and achieves ENOB of 7.7 bit. The ADC achieves FoM of 42.3 fJ/conversion in 0.13 μm CMOS technology.
Power consumption in SARADCs is greatly benefited by CMOS scaling due to its highly digital nature. However the power consumption in the capacitive DAC does not scale as well as the digital logic. In this thesis, two energy-efficient DAC switching techniques, Flip DAC and Quaternary capacitor switching, are proposed to reduce their energy consumption. Using these techniques, the energy consumption in the DAC can be reduced by 37 % and 42.5 % compared to the present state-of-the-art. A novel concept of code-independent energy consumption is introduced and emphasized. It mitigates energy consumption degradation with small input signal dynamic range.2018-02-22T18:30:00ZStudy on Pulsewidth Modulation Techniques for a Neutral-Point-Clamped Voltage Source Inverter
http://hdl.handle.net/2005/3169
Title: Study on Pulsewidth Modulation Techniques for a Neutral-Point-Clamped Voltage Source Inverter
Authors: Das, Soumitra
Abstract: Neutral-point-clamped (NPC) three-level inverter is capable of handling higher dc bus voltage and producing output waveform of better quality than a conventional two-level inverter. The main objective of the present work is to analyze the existing PWM schemes for two-level and three-level inverters in terms of line current ripple, and to design new PWM techniques for the NPC inverter to reduce line current distortion.
Various discontinuous PWM or bus-clamping PWM (BCPWM) methods for a two-level voltage source inverter are analyzed in terms of rms line current ripple, which is evaluated by integrating the error voltage (i.e. error between the applied and reference voltages). The BCPWM schemes can be broadly classified into continual-clamp PWM (CCPWM) and split-clamp PWM (SCPWM). It is shown that split-clamp PWM scheme leads to lower harmonic distortion than CCPWM scheme. Further, advanced bus-clamping PWM (ABCPWM) methods for a two-level inverter are also studied. These methods clamp each phase to the positive and negative DC terminals over certain intervals as in BCPWM schemes, and also switch each phase at double the nominal frequency in certain other intervals unlike in BCPWM. Analytical closed-form expressions are derived for the total rms harmonic distortion due to SCPWM, CCPWM and ABCPWM schemes.
Existing sinusoidal and bus-clamping PWM schemes for three-level NPC inverters are also analyzed in the space vector domain. These methods are compared in terms of line current ripple analytically as well as experimentally. As earlier, closed-form expressions are derived for the harmonic distortion factors corresponding to centered space vector PWM (CSVPWM) and the various BCPWM methods.
A three-level inverter can be viewed as an equivalent two-level inverter in each sixth of the fundamental cycle or hextant. This is widely used to simplify the control of an NPC inverter. Further, this approach makes it simple to extend the BCPWM and ABCPWM methods for two-level inverters to three-level inverters. Furthermore, the method of analysis of line current ripple for the two-level inverter can also be easily extended to the three-level case.
The pivot vector, which is half the length of the longest voltage vectors produced by the NPC inverter, acts as an equivalent null vector for the conceptual two-level inverter. Each pivot vector can be produced by two inverter states termed as “pivot states”. Typically, in continuous modulation methods for NPC inverter such as sinusoidal PWM and centered space vector PWM, the switching sequence (i.e. the sequence in which the voltage vectors are applied) begins and ends with the same pivot vector in each subcycle, which is equivalent to a half-carrier cycle. To be more precise, the switching sequence starts with one pivot state and ends with the other in each subcycle.
However, in case of BCPWM schemes, only one pivot state is used in a subcycle. The choice of pivot state results in a variety of BCPWM schemes for an NPC inverter. Different BCPWM schemes are evaluated in terms of rms line current ripple. The optimal BCPWM, which minimizes the rms current ripple, is determined for an NPC inverter, controlled as an equivalent two-level inverter.
Further, four new switching sequences are proposed here for a three-level inverter, controlled as a conceptual two-level inverter. These sequences apply the pivot vector only once, but employ one of the other two vectors twice within the subcycle. These four switching sequences are termed as “ABCPWM sequences” for three-level inverter. These sequences exploit the flexibility available in the space vector approach to PWM to switch a phase more than once in a subcycle, which results in the application of an active vector twice within the subcycle.
Influence of the proposed ABCPWM sequences on the line current ripple over a subcycle is studied. The various sequences are compared in terms of rms line current ripple over a subcycle. An analytical closed-form expression for rms line current ripple over a subcycle is derived in terms of reference magnitude, angle of reference voltage vector, and subcycle duration for each of the sequences. Further, closed-form expressions are also derived for the rms current ripple over a line cycle in terms of modulation index and subcycle duration, corresponding to the various sequences.
The four proposed ABCPWM sequences for the NPC inverter can be grouped into two pairs of sequences. Each pair of sequences is shown to perform better than the individual sequences, if the two sequences are employed in appropriate spatial regions. Hence, with these two pairs of sequences, two hybrid PWM schemes are proposed. Finally, a hybrid PWM technique is proposed which employs all five sequences (conventional and proposed four sequences) in spatial regions where each performs the best. This is termed as “five-zone hybrid PWM”. The total harmonic distortion (THD) in the motor current, pertaining to all the proposed schemes, is studied theoretically over the entire range of linear modulation.
The theoretical investigations are validated experimentally on a 2.2 kW, 415V, 4.9A, 50 Hz induction motor drive. The no-load current THD is measured over a range of fundamental frequency from 10 Hz to 50 Hz in steps of 2 Hz for the various PWM methods. Theoretical and experimental results bring out the reduction in current THD due to the proposed BCPWM schemes at fundamental frequencies of 45 Hz and above, compared to CSVPWM. The ABCPWM methods improve the performance at higher as well as lower modulation indices. Further improvement is achieved with the proposed five-zone hybrid PWM. At the rated frequency (50 Hz) of the drive, the improvement in line current distortion is around 36% with this hybrid PWM scheme over CSVPWM. The reduction in THD is also experimentally verified at different loads on the motor.
The difference between the top and bottom capacitor voltages is measured at various operating conditions, corresponding to CSVPWM and the proposed schemes. No significant difference is observed in the dc neutral voltage shifts with the different proposed schemes and CSVPWM method. Thus, the proposed methods improve the THD at low and high speed ranges without appreciable worsening of the dc voltage unbalance.2018-02-22T18:30:00ZReeb Graphs : Computation, Visualization and Applications
http://hdl.handle.net/2005/3173
Title: Reeb Graphs : Computation, Visualization and Applications
Authors: Harish, D
Abstract: Level sets are extensively used for the visualization of scalar fields. The Reeb graph of a scalar function tracks the evolution of the topology of its level sets. It is obtained by mapping each connected component of a level set to a point. The Reeb graph and its loop-free version called the contour tree serve as an effective user interface for selecting meaningful level sets and for designing transfer functions for volume rendering. It also finds several other applications in the field of scientific visualization.
In this thesis, we focus on designing algorithms for efficiently computing the Reeb graph of scalar functions and using the Reeb graph for effective visualization of scientific data. We have developed three algorithms to compute the Reeb graph of PL functions defined over manifolds and non-manifolds in any dimension. The first algorithm efficiently tracks the connected components of the level set and has the best known theoretical bound on the running time. The second algorithm, utilizes an alternate definition of Reeb graphs using cylinder maps, is simple to implement and efficient in practice. The third algorithm aggressively employs the efficient contour tree algorithm and is efficient both theoretically, in terms of the worst case running time, and practically, in terms of performance on real-world data. This algorithm has the best performance among existing methods and computes the Reeb graph at least an order of magnitude faster than other generic algorithms.
We describe a scheme for controlled simplification of the Reeb graph and two different graph layout schemes that help in the effective presentation of Reeb graphs for visual analysis of scalar fields. We also employ the Reeb graph in four different applications – surface segmentation, spatially-aware transfer function design, visualization of interval volumes, and interactive exploration of time-varying data.
Finally, we introduce the notion of topological saliency that captures the relative importance of a topological feature with respect to other features in its local neighborhood. We integrate topological saliency with Reeb graph based methods and demonstrate its application to visual analysis of features.2018-02-22T18:30:00ZSOI Based Integrated-Optic Microring Resonators for Biomedical Sensing Applications
http://hdl.handle.net/2005/3174
Title: SOI Based Integrated-Optic Microring Resonators for Biomedical Sensing Applications
Authors: Mangal, Nivesh
Abstract: Integrated Silicon Photonics has emerged as a powerful platform in the last
two decades amongst high-bandwidth technologies, particularly since the adop-
tion of CMOS compatible silicon-on-insulator(SOI) substrates. Microring res-
onators are one of the fundamental blocks on a photonic integrated circuit chip o ering versatility in varied applications like sensing, optical bu ering, ltering, loss measurements, lasing, nonlinear e ects, understanding cavity optomechanics etc.
This thesis covers the design and modeling of microring resonators for biosensing applications. The two applications considered are : homogeneous biosensing and wrist pulse pressure monitoring. Also, the designs have been used to fabricate ring resonator device using three different techniques. The results obtained through characterization of these devices are presented. Following are the observations made in lieu of this:
1) Design modeling and analysis - The analysis of ring resonator requires the study of both the straight and bent waveguide sections. Both rib and
strip waveguide geometries have been considered for constructing the device as
a building block by computing their respective eigen modes for both quasi-TE
and quasi-TM polarizations. The non-uniform evanescent coupling between the straight and curved waveguide has been estimated using coupled mode theory. This method provided in estimating the quality-factor and free spec-
tral range (FSR) of the ring-resonator. A case for optimizing the waveguide gap in the directional coupler section of a ring resonator has been presented for homogeneous biosensing application. On similar lines, a model of applying ring resonator for arterial pulse-pressure measurement has been analyzed. The results have been obtained by employing FD-BPM and FDTD including semi-
vectorial eigen mode solutions to evaluate the spectral characteristics of ring
resonator. The modeling and analytical results are supported by commercial
software tools (RSoft).
2) Fabrication and Characterization - For the fabrication, we employ
the design of ring resonator of radius 20 m on SOI substrate with two different waveguide gaps of 350 and 700 nm. Three different process sows have been used for fabricating the same device. The rst technique involved using negative e-beam resist HSQ which after exposure becomes SiO2, acts as a mask for Reactive-Ion Etching (RIE); helping in eliminating an additional step. The second technique involved the use of positive e-beam resist, PMMA for device patterning followed by metal deposition with lift-o . The third tech-
nique employed was Focussed Ion-beam (FIB) which is resist-less patterning
by bombarding Ga+ ions directly onto the top surface of the wafer with the help of a GDS le.
The characterization process involved estimation of loss and observing the be-
havior of optical elds in the device around the wavelength of 1550 nm using
near-field scanning optical microscopy (NSOM) measurement. The estimation of roughness-induced losses has been made by performing Atomic Force Microscopy (AFM) measurements.
In summary, the thesis presents novel design and analysis of SOI based microring resonators for homogeneous biosensing and wrist pulse pressure sensing
applications. Also, the fabrication and characterization of 20 m radius ring-
resonator with 500 500 nm rib cross-section is presented. Hence, this study
brings forth several practical issues concerning application of ring resonators
to biosensing applications.2018-02-22T18:30:00Z