http://hdl.handle.net/2005/17 2013-04-30T11:09:22Z http://hdl.handle.net/2005/1971 Title: Throughput Of Wireless Mesh Networks : An Experimental Study Authors: Ramachandran, P Abstract: Mesh network is gaining importance as the next generation network for many high speed applications such as multimedia streaming. This is because it is easy and inexpensive to setup mesh networks with mobile and PDA devices and can be used as a private network. Hence research is active in the field of routing protocols and routing metrics to improve the mesh network performance. Though most of the protocols are evaluated based on simulation, we implemented protocols based on a few metrics like Expected Transmission Count (ETX) Per-hop Packet Pair Delay (Pkt Pair) and WCETT (Weighted Cumulative Expected Transmitted Time) to investigate the performance of the network through experiments. An advanced version of DSR protocol called LQSR (Link Quality Source Routing) protocol of Microsoft Research along with MCL (Mesh Connectivity Layer) allows multiple heterogeneous adapters to be used in mesh network. Since wireless adapters of 802.11a standard offer 12 non-interfering channels and 802.11b/g standard offer 3 non-interfering channels, using multiple adapters of different bands operating on non-interfering channels to improve capacity and robustness of mesh networks was also investigated. In this thesis we explore the possibility of increasing the coverage area of Wireless Mesh Networks (WMN) to enhance the capacity of WMN and minimize the problems due to interference. Theoretical achievable capacity to every node in a random static wireless ad-hoc network with ideal routing is known to be where n is the total number of nodes in the network. Therefore, with increasing number of nodes in a network, throughput drops significantly. Our measurements show that throughput in a single WMN for different path length is closer to the throughput with nodes across two WMNs of the same path length. We propose to interconnect the networks by using multiple wireless adapters in a gateway node configured with the SSID of the networks in operation. We exploit the DSR protocol feature of assigning locally unique interface indices to its adapters. Performance of a network depends heavily on the metrics used for routing packets. Different metrics were studied in the thesis by setting up a 10-node testbed with a combination of nodes with single and two radios. Testbed was partitioned into two networks with two gateway nodes. Performance of multi-radio performance with the above metrics was compared with baseline single radio nodes in the network with the same metric. It is found that multi-radio nodes out-perform single radio nodes in the multi-hop scenario. Also, operating multi-mesh networks using multiple interfaces configured to those networks in a gateway node increases the coverage area and robustness without loss of performance. 2013-04-25T18:30:00Z http://hdl.handle.net/2005/1330 Title: Investigations On Boundary Selection For Switching Frequency Variation Control Of Current Error Space Phasor Based Hysteresis Controllers For Inverter Fed IM Drives Authors: Ramchand, Rijil Abstract: Current-Controlled Pulse Width Modulated (CC-PWM) Voltage Source Inverters (VSIs) are extensively employed in high performance drives (HPD) because of the considerable advantages offered by them, such as, excellent dynamic response and inherent over-current protection, as compared to the voltage-controlled PWM (VC-PWM) VSIs. Amongst the different types of CC-PWM techniques, hysteresis current controllers offer significant simplicity in implementation. However, conventional type of hysteresis controllers (with independent comparators) suffers from some well-known drawbacks, such as, limit cycle oscillations (especially at lower speeds of operation of machine), overshoot in current error, generation of sub-harmonic components in the current, and random (non-optimum) switching of inverter voltage vectors. Common problems associated with the conventional, as well as current error space phasor based hysteresis controllers with fixed bands (boundary), are the wide variation of switching frequency in the fundamental output cycle and variation of switching frequency with the change in speed of the load motor. These problems cause increased switching losses in the inverter, non-optimum current ripple, excess harmonics in the load current and subsequent additional machine heating. A continuously varying parabolic boundary for the current error space phasor is proposed previously to get the switching frequency variation pattern of the output voltage of the hysteresis controller based PWM inverter similar to that of voltage controlled space vector PWM (VC SVPWM) based VSI. But the major problem associated with this technique is the requirement of two outer parabolas outside the current error space phasor boundary for the identification of sector change which gives rise to some switching frequency variations in one fundamental cycle and over the entire operating speed range. It also introduces 5th and 7th harmonic components in the voltage causing 5th and 7th harmonic currents in the induction motor. These harmonic currents causes 6th harmonic torque pulsations in the machine. This thesis proposes a new technique which replaces the outer parabolas and uses current errors along orthogonal axes for detecting the sector change, so that a fast and accurate detection of sector change is possible. This makes the voltage harmonic spectrum of the proposed hysteresis controller based inverter exactly matching with that of a constant switching frequency SVPWM based inverter. This technique uses the property that the current error along one of the orthogonal axis changes its direction during sector change. So the current error never goes outside the parabolic boundary as in the case of outer parabolas based sector change technique. So the proposed new technique for sector change eliminates the 5th and 7th harmonic components from the applied voltage and thus eliminates the 5th and 7th harmonic currents in the motor. So there will be no introduction of 6th harmonic torque pulsations in the motor. Using the proposed scheme for sector change and parabolic boundary for current error space phasor, simulation study was carried out using Matlab-Simulink. Simulation study showed that the switching frequency variations in a fundamental cycle and over the entire speed range of the machine upto six step mode operation is similar to that of a VC-SVPWM based VSI. The proposed hysteresis controller is experimentally verified on a 3.7 kW IM drive fed with a two-level VSI using vector control. The proposed current error space phasor based hysteresis controller providing constant switching frequency is completely implemented on the TI TMS320LF2812 DSP controller platform. The three-phase reference currents are generated depending on the frequency command and the controller is tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are presented in this thesis. This thesis also proposes a new hysteresis controller which eliminates parabolic boundary and replaces it with a simple online computation of the boundary. In this proposed new hysteresis controller the boundary computed in the present sampling interval is used for identifying next vector to be switched. This thesis gives a detailed mathematical explanation of how the boundary is computed and how it is used for selecting vector to be switched in a sector. It also explains how the sector in which stator voltage vector is present is determined. The most important part of this proposed hysteresis controller is the estimation of stator voltages along alpha and beta axes during active and zero vector periods. Estimation of stator voltages are carried out using current errors along alpha and beta axes and steady state equivalent circuit of induction motor. Using this estimated stator voltages along alpha and beta axes, instantaneous phase voltages are computed and used for finding individual voltage vector switching times. These switching times are used for the computation of hysteresis boundary for individual vectors. So the hysteresis boundary for individual vectors are exactly calculated and used for vector change detection, making phase voltage harmonic spectrum exactly similar to that of constant switching frequency VC SVPWM inverter. Sector change detection is very simple, since we have the estimated stator voltages along alpha and beta axes to give exact position of stator voltage vector. Simulation study to verify the steady state as well as transient performance of the proposed controller based VSI fed IM drive is carried out using Simulink tool box of Matlab Simulation Software. The proposed hysteresis controller is experimentally verified on a 3.7 kW IM drive fed with a two-level VSI using vector control. The proposed current error space phasor based hysteresis controller providing constant switching frequency profile for phase voltage is implemented on the TI TMS320LF2812 DSP controller platform. The three-phase reference currents are generated depending on the frequency command and the proposed hysteresis controller is tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are presented for different operating conditions. 2011-08-03T18:30:00Z http://hdl.handle.net/2005/1408 Title: Power Optimal Network-On-Chip Interconnect Design Authors: Vikas, G Abstract: A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Hence, techniques to reduce interconnect power have become a necessity. In this thesis, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values. To validate our methodology, we implement the router design in 90 nm technology and measure power for various bus widths and frequency combinations. We find that the experimental results are in good agreement with the predicted theoretical results. Further, we present the scenario of an Application Specific System on Chip (ASSoC), where the throughput requirements are different on different links. We show that our analytical model holds in this case also. Then, we present modified version of the solution considered for Chip Multi Processor (CMP) case that can solve the ASSoC scenario also. 2011-09-07T18:30:00Z http://hdl.handle.net/2005/1271 Title: Formal Verification Of Analog And Mixed Signal Designs Using Simulation Traces Authors: Lata, Kusum Abstract: The conventional approach to validate the analog and mixed signal designs utilizes extensive SPICE-level simulations. The main challenge in this approach is to know when all important corner cases have been simulated. An alternate approach is to use the formal verification techniques. Formal verification techniques have gained wide spread popularity in the digital design domain; but in case of analog and mixed signal designs, a large number of test scenarios need to be designed to generate sufficient simulation traces to test out all the specified system behaviours. Analog and mixed signal designs can be formally modeled as hybrid systems and therefore techniques used for formal analysis and verification of hybrid systems can be applied to the analog and mixed signal designs. Generally, formal verification tools for hybrid systems work at the abstract level where we model the systems in terms of differential equations or algebraic equations. However the analog and mixed signal system designers are very comfortable in designing the circuits at the transistor level. To bridge the gap between abstraction level verification and the designs validation which has been implemented at the transistor level, the very important issue we need to address is: Can we formally verify the circuits at the transistor level itself? For this we have proposed a framework for doing the formal verification of analog and mixed signal designs using SPICE simulation traces in one of the hybrid systems formal verification tools (i.e. Checkmate from CMU). An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design to be also used for validating its different refinements and design implementation, thereby providing a simple route to formal verification at different levels of implementation. Our approach has been illustrated through the case studies using simulation traces form the different frameworks i.e. Simulink/Stateflow framework and the SPICE simulation traces. We demonstrate the feasibility of our approach around the Checkmate and the case studies for hybrid systems and the analog and mixed signal designs. 2011-07-07T18:30:00Z