etd AT Indian Institute of Science >
Division of Electrical Sciences >
Department of Electronic Systems Engineering (dese) >
Please use this identifier to cite or link to this item:
|Title: ||Random Local Delay Variability : On-chip Measurement And Modeling|
|Authors: ||Das, Bishnu Prasad|
|Advisors: ||Amrutur, Bharadwaj|
|Keywords: ||Electronic Gates - Design|
On-chip Management And Construction
Electronic Gate Delay - Modeling
Random Local Delay Variation
On-chip Gate Delay Measurement
Process Voltage And Temperature Gate Delay Model
Electronic Gate Delay - Measurement
Statistical Static Timing Analysis (SSTA)
Gate Delay Variability Measurement
Gate Delay Models
|Submitted Date: ||Jun-2009|
|Series/Report no.: ||G23404|
|Abstract: ||This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in silicon to study within-die variation. It also suggests a Process, Voltage and Temperature (PVT)-aware gate delay model for voltage and temperature scalable linear Statistical Static Timing Analysis (SSTA).
Technology scaling allows packing billions of transistors inside a single chip. However, it is difficult to fabricate very small transistor with deterministic characteristic which leads to variations. Transistor level random local variations are growing rapidly in each technology generation. However, there is requirement of quantification of variation in silicon. We propose an all-digital circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form based on a reconfigurable ring oscillator structure. A test chip is fabricated in 65nm technology node to show the feasibility of the technique. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations.
The huge random delay variation in silicon motivates the inclusion of random local process parameters in delay model. In today’s low power design with multiple supply domain leads to non-uniform supply profile. The switching activity across the chip is not uniform which leads to variation of temperature. Accurate timing prediction motivates the necessity of Process, Voltage and Temperature (PVT) aware delay model. We use neural networks, which are well known for their ability to approximate any arbitrary continuous function. We show how the model can be used to derive sensitivities required for voltage and temperature scalable linear SSTA for an arbitrary voltage and temperature point. Using the voltage and temperature scalable linear SSTA on ISCAS 85 benchmark shows promising results with average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.65% and errors in predicting the 99% and 1% probability point are 1.31% and 1% respectively with respect to SPICE.|
|Appears in Collections:||Department of Electronic Systems Engineering (dese)|
Items in etd@IISc are protected by copyright, with all rights reserved, unless otherwise indicated.