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Please use this identifier to cite or link to this item: http://hdl.handle.net/2005/1408

Title: Power Optimal Network-On-Chip Interconnect Design
Authors: Vikas, G
Advisors: Varghese, Kuruvilla
Kuri, Joy
Keywords: Network On Chip - Design and Construction
Electric Power Networks
Application Specific System On Chip
Routers (Computer Networks)
Chip Multi Core Processor
Network-on-Chip Interconnect Design
Submitted Date: Feb-2010
Series/Report no.: G23700
Abstract: A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Hence, techniques to reduce interconnect power have become a necessity. In this thesis, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values. To validate our methodology, we implement the router design in 90 nm technology and measure power for various bus widths and frequency combinations. We find that the experimental results are in good agreement with the predicted theoretical results. Further, we present the scenario of an Application Specific System on Chip (ASSoC), where the throughput requirements are different on different links. We show that our analytical model holds in this case also. Then, we present modified version of the solution considered for Chip Multi Processor (CMP) case that can solve the ASSoC scenario also.
Abstract file URL: http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf
URI: http://etd.iisc.ernet.in/handle/2005/1408
Appears in Collections:Department of Electronic Systems Engineering (dese)

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