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Please use this identifier to cite or link to this item: http://hdl.handle.net/2005/1532

Title: Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors
Authors: Valluri, Madhavi Gopal
Advisors: Govindarajan, R
Keywords: Compiling (Electronic Computers)
Instruction Scheduling
Register Allocation
Machine Models
Instruction-Level Parallelism (ILP)
Very Long Instruction Word (VLIW) Processors
Modulo-Variable Expansion (MVE)
Sensitive Scheduling
Submitted Date: Jan-1999
Series/Report no.: G23229
Abstract file URL: http://etd.ncsi.iisc.ernet.in/abstracts/1959/G15406-Abs.pdf
URI: http://etd.iisc.ernet.in/handle/2005/1532
Appears in Collections:Supercomputer Education and Research Centre (serc)

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