
etd AT Indian Institute of Science >
Division of Electrical Sciences >
Department of Electronic Systems Engineering (dese) >
Please use this identifier to cite or link to this item:
http://hdl.handle.net/2005/2600

Title:  Investigation On Dodecagonal Multilevel Voltage Space Vector Structures By Cascading Flying Capacitor And Floating HBridge Cells For Medium Voltage IM Drives 
Authors:  Mathew, Jaison 
Advisors:  Gopakumar, K 
Keywords:  Induction Motors Two Level Inverters Multilevel Inverters Induction Electric Motors HBridge Cells Induction Motor Drives Voltage Space Vectors Space Vector Pulse Width Modulation Dodecagonal Space Vector Multilevel Inverters Multilevel Inverter Topologies Dodecagonal Space Vectors Flying Capacitor Multilevel Inverters High Power Medium Voltage Drives HBridge Multilevel Inverters Multilevel Inverters Pulse Width Modulation Flying Capacitor Topology IM Drives 
Submitted Date:  Jul2013 
Series/Report no.:  G26019 
Abstract:  In highpower electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of subharmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutralpointclamped (NPC) inverters, cascaded Hbridge, and flyingcapacitor multilevel inverters are some of the popular schemes used for highpower applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (openend winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic twolevel VSI topology.
The inverters used in motor drive applications have to be operated in overmodulation range in order to extract the maximum fundamental output voltage that is possible from the dclink. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these loworder harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these loworder harmonics and nonlinear PWM operation in overmodulation region, frequent overcurrent fault conditions occur and reliability of the drive is jeopardized. The twelve sidedpolygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal spacevector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform.
Most of the previous works of dodecagonal spacevector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutralpoint voltage fluctuation and the neutralpoint voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal spacevector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point chargebalancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors.
For the speed control of induction motors, the spacevector PWM scheme is more advantageous than the sinetriangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional spacevector PWM is that the trigonometric operations demand formidable computational efforts and lookup tables. Carrier based, commonmode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. Information regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is proposed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large lookup tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrierbased methods).
The openend winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal spacevector structures relied on induction motors with openend windings. The main disadvantage of openend winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter2 of this thesis uses openend winding motor with flyingcapacitor inverters for the generation of dodecagonal spacevectors, the topology presented in chapter3 utilizes a cascade connection of flyingcapacitors and floating Hbridge cells to generate the same set of voltage spacevectors, thus allowing any standard induction motor as the load.
Of the methods used for the speed control of induction motors, namely sinetriangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a wellunderstood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage spacevector based multilevel inverter drives. In chapter4 of the thesis, this aspect is taken into account and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance.
The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a fourpole, 3.7kW, 50Hz, 415V threephase induction motor was used as the load. Since the PWM ports are limited in a DSP, a ﬁeldprogrammable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the deadtime signals for the power devices also. 
Abstract file URL:  http://etd.ncsi.iisc.ernet.in/abstracts/3396/G26019Abs.pdf 
URI:  http://etd.iisc.ernet.in/handle/2005/2600 
Appears in Collections:  Department of Electronic Systems Engineering (dese)

Items in etd@IISc are protected by copyright, with all rights reserved, unless otherwise indicated.
