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|Title: ||Power-Aware Compilation Techniques For Embedded Systems|
|Authors: ||Shyam, K|
|Advisors: ||Govindarajan, R|
|Keywords: ||Electric Power Control|
Computer Memory Architecture
Dynamic Voltage Scaling
Integer Linear Programming (ILP)
|Submitted Date: ||Jul-2006|
|Abstract: ||The demand for devices like Personal Digital Assistants (PDA’s), Laptops, Smart Mobile
Phones, are at an all time high. As the demand for these devices increases, so is the push to provide sophisticated functionalities in these devices. However energy consumption has become a major constraint in providing increased functionality for these devices. A majority of the applications meant for these devices are rich with multimedia content.
In this thesis, we propose two approaches for compiler directed energy reduction, one
targeting the memory subsystem and another the processor.
The ﬁrst technique is a compiler directed optimization technique that reduces the
energy consumption of the memory subsystem, for an oﬀ-chip partitioned memory archi-
tecture, having multiple memory banks, and various low-power operating modes for each
of these banks. We propose an eﬃcient layout of the data segment to reduce the number
of simultaneously active memory banks, so that the other memory banks that are inactive
can be put to low power modes to reduce the energy. We model this problem as a graph
partitioning problem, and use well known heuristics to solve the same. We also propose
a simple Integer Linear Programming (ILP) formulation for the above problem. Perfor-
mance results indicate that our approach achieves an energy reduction of 20% compared
to the base scheme, and a reduction of 8%-10% over a previously suggested method. Also,
our results are well within the optimal results obtained by using ILP method.
The second approach proposed in this thesis reduces the dynamic energy consumed by the processor using dynamic voltage and frequency scaling technique. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chieﬂy on loop nests and/or subroutine
calls having suﬃcient number of dynamic instructions. We concentrate on coarser pro-
gram regions and for the ﬁrst time uses program phase behavior for performing dynamic
voltage scaling. We relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it eﬃciently. Also, we develop a simple Integer Linear Programming (ILP) problem formulation for this problem. Experi-mental evaluation on a set of media applications reveal that our heuristic method obtains 35-40% reduction in energy consumption on an average, with a negligible performance degradation. Further the energy consumed by our heuristic solution is within 1% the optimal solution obtained by the ILP approach.|
|Appears in Collections:||Supercomputer Education and Research Centre (serc)|
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