etd AT Indian Institute of Science >
Division of Electrical Sciences >
Department of Electronic Systems Engineering (dese) >
Please use this identifier to cite or link to this item:
|Title: ||Current-Mode Techniques In The Synthesis And Applications Of Analog And Multi-Valued Logic In Mixed Signal Design|
|Authors: ||Bhat, Shankaranarayana M|
|Advisors: ||Jamadagni, H S|
|Keywords: ||Signal Processing - Digital Techniques|
Multiple-Valued Logic (MVL)
Complementary Metal Oxide Semiconductors
|Submitted Date: ||Nov-2006|
|Abstract: ||The development of modern integration technologies is normally driven by the needs of digital CMOS circuit design. Rapid progress in silicon VLSI technologies has made it possible to implement multi-function and high performance electronic circuits on a single die. Coupled with this, the need for interfacing digital blocks to the external world resulted in the integration of analog blocks such as A/D and D/A converters, ﬁlters and oscillators
with the digital logic on the same die. Thus, mixed signal system-on-chip (SOC) solutions are becoming a common practice in the present day integrated circuit (IC) technologies.
In digital domain, aggressive technology scaling redeﬁnes, in many ways, the role
of interconnects vis-`a-vis the logic in determining the overall performance. Apart from signal integrity, power dissipation and reliability issues, delays over long interconnects far exceeding the logic delay becomes a bottleneck in high speed operation. Moreover, with an increasing density of chips, the number of interchip connections is greatly increased as more and more functions are put on the same chip; thus, the size and performance of the chip are mostly dominated by wiring rather than devices. One of the most promising approaches to solve the above interconnection problems is the use of multiple-valued logic (MVL) inside the chip [Han93, Smi88]. The number of interconnections can be directly reduced with multiple valued signal representation. The reduced complexity of interconnections makes the chip area and delay much smaller leading to reduced cross talk noise and improved reliability. Thus, the inclusion of multiple-valued logic in a otherwise mixed design, consisting of analog and binary logic, can make the transition from analog
to digital world much more smoother and at the same time improve the overall system
As the sizes of integrated devices decrease, maximum voltage ratings also rapidly
decrease. Although decreased supply voltages do not restrict the design of digital circuits, it is harder to design high performance analog and multiple valued integrated circuits using new processes. As an alternative to voltage-mode signal processing, current-mode circuit techniques, which use current as a signal carrier, are drawing strong attention today due to their potential application in the design of high-speed mixed-signal processing circuits
in low-voltage standard VLSI CMOS technologies. Industrial interest in this ﬁeld has been propelled by the proposal of innovative ideas for ﬁlters, data converters and IC prototypes in the high frequency range [Tou90, Kol00]. Further, in MVL design using conventional CMOS processing, diﬀerent current levels can be easily used to represent diﬀerent logic values. Thus the case for an integrated approach to the design of analog, multi-valued and binary logic circuits using current-mode techniques seems to be worth considering.
The work presented in this thesis is an effort to reaffirm the utility of current-mode circuit techniques to some of the existing as well as to some new areas of circuit design. We present new algorithms for the synthesis of a class of analog and multiple-valued logic circuits assuming an underlying CMOS current-mode building blocks. Next we present quaternary current-mode signaling scheme employing a simple encoder and decoder architecture for improving the signal delay characteristics of long interconnects in digital logic blocks. As an interface between analog and digital domain, we present an architecture of
current-mode ﬂash A/D converter. Finally, low power being a dominant design constraint
in today IC technology, we present a scheme for static power minimization in a class of
|Appears in Collections:||Department of Electronic Systems Engineering (dese)|
Items in etd@IISc are protected by copyright, with all rights reserved, unless otherwise indicated.