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Please use this identifier to cite or link to this item: http://hdl.handle.net/2005/397

Title: A Systematic Approach To Synthesis Of Verification Test-Suites For Modular SoC Designs
Authors: Surendran, Sudhakar
Advisors: Govindarajan, R
Keywords: Microcomputer Chips - Testing And Measurement
Microcomputer Circuits - Testing And Measurement
System On Chips (SoC)
Memory Test-Case Generation
Data Transfer Test-Case Generation
SoC - Design - Verification
Submitted Date: Nov-2006
Series/Report no.: G20903
Abstract: SoCs (System on Chips) are complex designs with heterogeneous modules (CPU, memory, etc.) integrated in them. Verification is one of the important stages in designing an SoC. Verification is the process of checking if the transformation from architectural specification to design implementation is correct. Verification involves creating the following components: (i) a testplan that identifies the conditions to be verified, (ii) a testcase that generates the stimuli to verify the conditions identified, and (iii) a test-bench that applies the stimuli and monitors the output from the design. Verification consumes upto 70% of the total design time. This is largely due to the complex and manual nature of the verification task. To reduce the time spent in verifying the design, the components used for verification can be generated automatically or created at an abstract level (to reduce the complexity) and reused. In this work we present a methodology to synthesize testcases from reusable code segments and abstract specifications. Our methodology consists of the following major steps: (i) identifying the structure of testcases, (ii) identifying code segments of testcases that can be reused from one SoC to another, (iii) identifying properties of an SoC and its modules that can be used to synthesize the SoC specific code segments of the testcase, and (iv) proposing a synthesizer that uses the code segments, the properties and the abstract specification to synthesize testcases. We discuss two specific classes of testcases. These are testcases for verifying the memory modules and the testcases for verifying the data transfer modules. These are considered since they form a significantly large subset of the device functionality. We implement a prototype testcase generator and also present an example to illustrate the use of methodology for each of these classes. The use of our methodology enables (i) the creation of testcases automatically that are correct by construction and (ii) reuse of the testcase code segments from one SoC to another. Some of the properties (of the modules and the SoC) presented in our work can be easily made part of the architectural specification, and hence, can further reduce the effort needed to create them.
URI: http://hdl.handle.net/2005/397
Appears in Collections:Supercomputer Education and Research Centre (serc)

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