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Please use this identifier to cite or link to this item: http://hdl.handle.net/2005/666

Title: Impact Of Energy Quantization On Single Electron Transistor Devices And Circuits
Authors: Dan, Surya Shankar
Advisors: Mahapatra, Santanu
Keywords: Transistor Devices (Electronics)
Energy Quantization
Inverter Logic
Single Electron Transistor (SET)
Monte Carlo Simulation
Orthodox Theory
Compact Modeling
Single Electron Tunneling
Noise Margin
SET Circuits
Single Electron Inverter Performance
Coulomb Blockade
Negative Differential Resistance
Submitted Date: Mar-2009
Series/Report no.: G23077
Abstract: Although scalingof CMOS technology has been predicted to continue for another decade, novel technological solutions are required to overcome the fundamental limitations of the decananometer MOS transistors. Single Electron Transistor (SET) has attracted attention mainly because of its unique Coulomb blockade oscillations characteristics, ultra low power dissipation and nanoscale feature size. Despite the high potential, due to some intrinsic limitations (e.g., very low current drive) it will be very difficult for SET to compete head-to-head with CMOS’s large-scale infrastructure, proven design methodologies, and economic predictability. Nevertheless, the characteristics of SET and MOS transistors are quite complementary. SET advocates low-power consumption and new functionality (related to the Coulomb blockade oscillations), while CMOS has advantages like high-speed driving and voltage gain that can compensate the intrinsic drawbacks of SET. Therefore, although a complete replacement of CMOS by single-electronics is unlikely in the near future, it is also true that combining SET and CMOS one can bring out new functionalities, which are unmirrored in pure CMOS technology. As the hybridization of CMOSand SET is gaining popularity, silicon SETs are appearing to be more promising than metallic SETs for their possible integration with CMOS. SETs are normally studied on the basis of the classical Orthodox Theory, where quantization of energy states in the island is completely ignored. Though this assumption greatly simplifies the physics involved, it is valid only when the SET is made of metallic island. As one cannot neglect the quantization of energy states in a semi conductive island, it is extremely important to study the effects of energy quantization on hybrid CMOSSET integrated circuits. The main objectives of this thesis are: (1) understand energy quantization effects on SET by numerical simulations; (2) develop simple analytical models that can capture the energy quantization effects; (3)analyze the effects of energy quantization on SET logic inverter, and finally; (4)developa CAD framework for CMOS-SETco-simulation and to study the effects of energy quantization on hybrid circuits using that framework. In this work the widely accepted SIMON Monte Carlo (MC) simulator for single electron devices and circuits is used to study the effects of energy quantization. So far SIMON has been used to study SETs having metallic island. In this work, for the first time, we have shown how one can use SIMON to analyze SET island properties having discrete energy states.It is shown that energy quantization mainly changes the Coulomb Blockade region and drain current of SET devices and thus affects the noise margin, power dissipation, and the propagation delay of SET logic inverter. Anew model for the noise margin of SET inverter is proposed, which includes the energy quantization term. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termedas “Quantization Threshold”)that an SET inverter logic circuit can withstand before its noise margin upper bound crosses the acceptable tolerance limit. It is found that SET inverter designed with CT : CG =0.366 (where CT and CG are tunnel junction and gate capacitances respectively) offers maximum robustness against energy quantization. Then the effects of energy quantization are studied for Current biased SET (CBS), which is an integral part of almost all hybrid CMOS-SET circuits. It is demonstrated that energy quantization has no impact on the gain of the CBS characteristics though it changes the output voltage levels and oscillation periodicity. The effects of energy quantization are further studied for two circuits: Negative Differential Resistance (NDR) and Neurone Cell, which use CBS. A new model for the conductance of NDR characteristics is also formulated that includes the energy quantization term. A novel CAD framework is then developed for CMOS-SET co-simulation, whichuses MCsimulator for SET devices alongwithconventional SPICE. Using this framework, the effects of energy quantization are studied for some hybrid circuits, namely, SETMOS, multiband voltage filter, and multiple valued logic circuits. It is found that energy quantization degrades the performance of hybrid circuit, which could be compensated by properly tuning the bias current of SET devices. Though this study is primarily done by exhaustive MC simulation, effort has also been put to develop first order compact model for SET that includes energy quantization effects. Finally it has been demonstrated that the SET behavior under energy quantization can be predicted byslightlymodifyingthe existing SETcompact models that are valid for metallic devices having continuous energy states.
URI: http://hdl.handle.net/2005/666
Appears in Collections:Department of Electronic Systems Engineering (dese)

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